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Название: Delay Insensitive Circuits : Structures, Semantics, and Strategies (Update 2023-06-17)
Автор: Dennis Furey
Издательство: Plumstead Publishing House
Год: 2023-06-16
Страниц: 652
Язык: английский
Формат: pdf (true)
Размер: 114.3 MB
Delay insensitive circuits rely on local coordination and control from the ground up, enabling data and signal processing applications without any clock distribution network whatsoever. This ability can bring a welcome relief to projects whose timing infrastructure would otherwise tend to create more problems than it solves. The quest for performant, robust electronics for data and signal processing applications has often depended on the help of a small close-knit faction of specialists in asynchronous circuit design working on the margins of the broader engineering community. On those rare but dreaded occasions when its technical debt comes due, the deeply held assumption of discrete global time in synchronous design (as opposed to asynchronous design) harshly reaffirms the need for their esoteric skills. Sometimes incremental progress is achievable by a combination of synchronous and asynchronous circuitry carefully organized as far as possible to insulate the majority of engineers from unwelcome contingencies. Field Programmable Gate Arrays (FPGA) would seem ideally situated to attract similar interest, but have achieved only limited success in that regard at best. Although undoubtedly due in part to the marketing focus on commercial developers by the major FPGA vendors, this unfortunate circumstance might be more aptly explained by the hard truth that FPGA programming is a little too much like work to fit most people’s idea of a recreational activity.
Автор: Dennis Furey
Издательство: Plumstead Publishing House
Год: 2023-06-16
Страниц: 652
Язык: английский
Формат: pdf (true)
Размер: 114.3 MB
Delay insensitive circuits rely on local coordination and control from the ground up, enabling data and signal processing applications without any clock distribution network whatsoever. This ability can bring a welcome relief to projects whose timing infrastructure would otherwise tend to create more problems than it solves. The quest for performant, robust electronics for data and signal processing applications has often depended on the help of a small close-knit faction of specialists in asynchronous circuit design working on the margins of the broader engineering community. On those rare but dreaded occasions when its technical debt comes due, the deeply held assumption of discrete global time in synchronous design (as opposed to asynchronous design) harshly reaffirms the need for their esoteric skills. Sometimes incremental progress is achievable by a combination of synchronous and asynchronous circuitry carefully organized as far as possible to insulate the majority of engineers from unwelcome contingencies. Field Programmable Gate Arrays (FPGA) would seem ideally situated to attract similar interest, but have achieved only limited success in that regard at best. Although undoubtedly due in part to the marketing focus on commercial developers by the major FPGA vendors, this unfortunate circumstance might be more aptly explained by the hard truth that FPGA programming is a little too much like work to fit most people’s idea of a recreational activity.