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
Автор: Bernard Goossens
Издательство: Springer
Серия: Undergraduate Topics in Computer Science
Год: 2023
Страниц: 451
Язык: английский
Формат: pdf (true)
Размер: 14.7 MB
This book is a new textbook on processor architecture. What is new is not the topic, even though actual multicore and multithreaded designs are depicted, but the way processor architecture is presented. The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore). Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board. The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators.