Название: Guide to Computer Processor Architecture: A RISC-V Approach, With High-level Synthesis
Автор: Bernard Goossens
Издательство: Springer
Серия: Undergraduate Topics in Computer Science
Год: 2023
Страниц: 451
Язык: английский
Формат: pdf (true)
Размер: 14.7 MB

This book is a new textbook on processor architecture. What is new is not the topic, even though actual multicore and multithreaded designs are depicted, but the way processor architecture is presented. The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore).

Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board (such a board can be freely obtained from the Xilinx University Program targeting the university professors). The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators.

Two improvements in computer hardware and software made it eventually feasible: the availability of personal computers and the C programming language. They give the full access to the hardware. Nowadays, an FPGA plays the role of the personal computer of the 70s: It gives access to the logic gates. The High-Level Synthesis tool (HLS) plays the role of the C compiler of the 70s: It gives access to the FPGA through a high-level language.

The book is divided into two parts and 14 chapters, including an introduction and a conclusion. Part I, from Chaps. 1 to 10, is devoted to single core processors. Part II, from Chaps. 11 to 14, presents some multicore implementations:

Chapter 1 is the introduction. It presents what an FPGA is and how HLS works to transform a C program into a bitstream to configure the FPGA.
The two following chapters give the necessary indications to build the full environment used in the book to develop the RISC-V processors.
Chapter 2 is related to the Xilinx Vitis FPGA tools (the Vitis_HLS FPGA synthesizer, the Vivado FPGA integrator, and the Vitis IDE FPGA programmer).
Chapter 3 presents the RISC-V tools (the Gnu toolchain, the Spike simulator, and the OpenOCD/gdb debugger), their installation, and the way to use them.
Chapter 4 presents the RISC-V architecture (more precisely, the RV32I ISA) and the assembly language programming.
Chapter 5 shows the three main steps in building a processor: fetching, decoding, and executing. The construction is incremental. The general principles of HLS programming, in contrast to classic programming, are explained in the first section of Chap. 5.
Chapter 6 completes chapter five with the addition of a data memory to fulfill the first RISC-V processor IP. The implemented microarchitecture has the most simple non-pipelined organization.
...
Chapter 12 presents a multicore IP based on the multicycle six-stage pipeline. The IP can host from two to eight cores running either independent applications or parallelized ones.
Chapter 13 shows a multicore multihart IP. The IP can host two cores with four harts each or four cores with two harts each.
Chapter 14 concludes by showing how you can use your RISC-V processor implementations to play with your development board, lighting LEDs (Light-Emitting Diode) as push buttons are pressed.




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