Название: Completion Detection in Asynchronous Circuits: Toward Solution of Clock-Related Design Challenges
Автор: Pallavi Srivastava
Издательство: Springer
Год: 2022
Страниц: 129
Язык: английский
Формат: pdf (true), epub
Размер: 21.2 MB

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.

Asynchronous design style has experienced a renaissance in recent decades, as the demand for smaller, faster circuits exacerbates the challenges associated with clock distribution, clock skew and other clock-related issues in synchronous circuits. Asynchronous circuits are inherently free from challenges associated with clock signals, as they do not use clock signal(s) to indicate the process completion and instead use handshaking signals to communicate between two asynchronous logic blocks. Using handshaking signals provides an opportunity for the designers of asynchronous circuits to determine the process completion based on the actual input data rather than having to wait for a critical path delay for each computation, as would be the case with a global clock. Hence, asynchronous circuits can utilise the average-case computation delay as they have event-driven characteristics and can indicate data validity as soon as the computation is done, but detecting the completion of the computational process has always been a challenge in such circuits.

Existing completion detection schemes utilise either bundled data or dual-rail data encoding techniques to detect the completion of an event. Most of the researchers prefer dual-rail coding to implement asynchronous circuits even though it needs a large silicon area because it can indicate data validity deterministically. On the other hand, the silicon area required by bundled data protocol is comparable to synchronous design, but it opts for the worst-case delay model to determine the completion of an event. This trade-off between area and speed is eliminated by the completion detection scheme introduced in this book since it can deterministically determine the completion of an event for bundled data circuits. The generic architecture of the deterministic completion detection scheme was developed in accordance with the characteristics of the input data and can be implemented for any asynchronous bundled data circuit that fits a certain set of requirements. When designing a digital circuit, the availability of a generic architecture enables researchers to make an informed choice between synchronous and asynchronous design styles.




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