Название: Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package
Автор: Beth Keser, Steffen Kröhnert
Издательство: Wiley-IEEE Press
Год: 2022
Страниц: 323
Язык: английский
Формат: pdf (true)
Размер: 20.3 MB

Discover an up-to-date exploration of Embedded and Fan-Out Waver and Panel Level technologies.

In Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces: High Performance Compute and System-in-Package, a team of accomplished semiconductor experts delivers an in-depth treatment of various fan-out and embedded die approaches.

The book begins with a market analysis of the latest technology trends in Fan-Out and Wafer Level Packaging before moving on to a cost analysis of these solutions. The contributors discuss the new package types for advanced application spaces being created by companies like TSMC, Deca Technologies, and ASE Group. Finally, emerging technologies from academia are explored.

In the twenty-first century, newly emerged end-user systems in consumer electronics and mobile devices have become the core pillars of modernized progress and economic growth. One major evolution of mobile devices is the smartphone. Diversified application needs coupled with the slowing down of Moore’s law has turned the attention of the semiconductor industry to advanced packaging technology for enhanced system-level performance and functionality as well as a smaller form factor, reduced power consumption, and cost-effectiveness. In fact, key platforms of advanced packaging technologies, such as flip-chip, fan-out (FO), and fan-in, have enabled better performance with new functionality, all achieved in the smaller form factor that makes today’s sleek yet powerful smartphone a reality.

Since 2000, there has been a widespread adoption of wafer-level packaging (WLP), in which most of the packaging and testing is accomplished in full wafer form. WLP does not require an intermediate integrated circuit (IC) substrate, thus allowing a thinner package profile, and it can be directly mounted onto the motherboard. Specific to fan-out packaging (FO) are interconnects that go beyond the chip edge and allow multi-chip and 2.5D and 3D packaging solutions. FO technology can be used to fabricate a redistribution layer (RDL) interposer, which is a low-cost alternative to 2.5D packaging. Also, FO technology facilitates multi-die stacking in the vertical direction to enable 3D packaging solutions. These benefits of input/output (IO) density scalability and the integration of passive and active chips in the same package with drastic miniaturization potential by means of 2D, 2.5D, and 3D structures have made FO one of the top options in semiconductor packaging.

Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces is an indispensable resource for microelectronic package engineers, managers, and decision makers working with OEMs and IDMs. It is also a must-read for professors and graduate students working in microelectronics packaging research.




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