Название: Wireless Interface Technologies for 3D IC and Module Integration
Автор: Tadahiro Kuroda, Wai-Yeung Yip
Издательство: Cambridge University Press
Год: 2021
Страниц: 338
Язык: английский
Формат: pdf (true)
Размер: 20.9 MB

Synthesising fifteen years of research, this authoritative text provides a comprehensive treatment of two major technologies for wireless chip and module interface design, covering technology fundamentals, design considerations and tradeoffs, practical implementation considerations, and discussion of practical applications in neural network, reconfigurable processors, and stacked SRAM. It explains the design principles and applications of two near-field wireless interface technologies for 2.5-3D IC and module integration respectively, and describes system-level performance benefits, making this an essential resource for researchers, professional engineers and graduate students performing research in next-generation wireless chip and module interface design.

In the last 35 years, integrated circuit (IC) feature size was reduced by more than two orders of magnitude. However, operating voltage has been reduced by only an order of magnitude. This is because the electric field required to switch the transistor gate does not scale down linearly. Process scaling without proportional reduction in operating voltage has resulted in a three-orders-of-magnitude increase in power density. Consequently, power density has become a limiting factor in IC performance improvement.

Another challenge to the advance of IC is the integration of heterogeneous chip technologies. For example, while logic functions demand high-performance transistors, memory storage requires high-density capacitors. If both functions are integrated onto a single chip, the manufacturing cost can become prohibitively high. As a result, logic and memory are implemented on separate chips with independently optimized processes, and the interface between the two through which data flow has become a bottleneck in information processing. Consequently, a key to further computing system performance improvement is in developing the chip interface, so as to improve power efficiency by optimizing the interconnection, and to remove the bottleneck in data transmission.

This discussion of the evolution of the IC, the chip interface, the computer, plus the connector, and the associated challenges is elaborated in Chapter 1. Its summary points to a need to shift chip interconnection from two dimensions (2D) to three dimensions (3D). The timing for a revolutionary interface is right, since the slowing of Moore’s law has created an opportunity to introduce disruptive technologies to deliver more than Moore performance leaps.




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